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| FUJITSU SEMICONDUCTOR DATA SHEET DS07-12528-3E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89143A/144A Series MB89143A/144A s DESCRIPTION The MB89143A/144A has been developed as a general-purpose version of the F2MC-8L* family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain peripheral functions such as dual-clock control system, five operating speed control stages, timers, a serial interface, an A/D converter, buzzer output, high voltage driver, watch prescaler, and an external interrupt. The MB89143A/144A is applicable to a wide range of applications from welfare products to industrial equipment. *: F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES * Minimum execution time: 0.50 s/8.0-MHz oscillation * Interrupt servicing time: 4.50 s/8.0-MHz oscillation * F2MC-8L family CPU core Multiplication and division instructions Instruction set optimized for controllers 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. * Dual-clock control system * High-voltage ports: 24 channel (Continued) s PACKAGE 64-pin Plastic SH-DIP (DIP-64P-M01) MB89143A/144A (Continued) * Two types of timers 8/16-bit timer/counter (also usable as two 8-bit timers) 21-bit time-base timer * One 8-bit serial interface Switchable transfer direction allows communication with various equipment. * 8-bit A/D converter: 8 channels Successive approximation type * External interrupt: 2 channels Two channels are independent and capable of wake-up from low-power consumption modes. (Rising edge/ falling edge/both edges selectability) -0.3 V to +7.0 V can be applied to INT1 (N-ch open-drain) * Low-power consumption modes Subclock mode (The main clock stops, and the device operates at the subclock.) Watch mode (Only the watch prescaler is operating.) Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) * Watch prescaler * Buzzer output * Watchdog reset, reset output, and power-on reset functions 2 MB89143A/144A s PRODUCT LINEUP Part number Parameter MB89143A MB89144A MB89P147 One-time PROM product 32 K x 8 bits Internal PROM 1 K x 8 bits Internal MB89PV140 Piggyback/evaluation product (for evaluation and development) Classification ROM size Mass production products (mask ROM products) 8 K x 8 bits 12 K x 12 bits 32 K x 8 bits External ROM (Piggyback) RAM size CPU functions 256 x 8 bits Number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum execution time: 0.5 s/8 MHz to 8.0 s/8 MHz, 61 s/32.768 kHz Interrupt processing time: 4.5 s/8 MHz to 72.0 s/8 MHz, 562.5 s/32.768 kHz Note: The above times change according to the gear function. High-voltage output ports (P-ch open-drain): 24 (P40 to P47, P50 to P57, and P60 to P67) Buzzer output (P-ch open-drain, high-voltage):1 Output ports (CMOS): 4 (P20 to P23) Input ports (CMOS): 2 (P70 and P71, function as X0A and X1A pins when dual-clock system is used.) I/O ports (CMOS): 23 (P00 to P07, P10 to P17, P30, and P32 to P37) I/O port (N-channel open-drain): 1 (P31) Total: 55 Capable of generating four different intervals (at 8.0-MHz oscillation): 0.26 ms, 0.51 ms, 1.02 ms, and 0.524 s 8/16-bit timer operation (Operating clock, internal clock, external trigger) 8/16-bit event counter operation (Rising edge/falling edge/both edges selectability) 8 bits LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 4, 8, 16 system clock cycles) 8-bit resolution x 8 channels A/D conversion mode (with conversion time of 22 s/8 MHz, and highest gear speed) Continuous activation by external activation capable 10-bit resolution x 12 channels A/D conversion mode (with conversion time of 16.5 s/ 8 MHz, and highest gear speed) Sense mode (with conversion time of 9.0 s/8 MHz, and highest gear speed) Continuous activation enabled by external activation capable Ports Time-base timer 8/16-bit timer counter 8-bit Serial I/O A/D converter External interrupt 2 independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge/both edges selectability Built-in analog noise canceller Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) Buzzer output 1.95 or 3.91 kHz selectable (at 8-MHz oscillation) Output to a high-voltage pin (Continued) 3 MB89143A/144A (Continued) Part number Parameter MB89143A MB89144A MB89P147 MB89PV140 Watchdog reset 8-bit PWM timer 12-bit MPG timer Standby mode Process Package EPROM for use Operating voltage* Internal reset in 524 ms to 1049 ms (at 8 MHz oscillation) when the program runway occurs None None 8-bit timer operation/8-bit resolution PWM operation 12-bit resolution PWM operation/reload timer operation/PPG operation Sleep mode, stop mode, and watch mode CMOS DIP-64P-M01 4.0 V to 6.0 V MDP-64C-P02 MBM27C256A-20 2.7 V to 6.0 V * : Varies with conditions such as the operating frequency. (See section "s ELECTRICAL CHARACTERISTICS".) s PACKAGE AND CORRESPONDING PRODUCTS Package DIP-64P-M01 MDP-64C-P02 : Available x x: Not available x MB89143A MB89144A MB89P147 MB89PV140 x Note: For more information about each package, see section "s PACKAGE DIMENSION". 4 MB89143A/144A s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: * On the MB89143A/144A, the upper half of the register bank cannot be used. * The stack area etc. are set at the upper limit of the RAM. 2. Functions Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following point: * The A/D converter in the MB89143A/144A is an 8-bit resolution type. The MB89143A/144A contains neither the 8-bit PWM timer nor the 12-bit MPG timer. 3. Current Consumption * In the case of the MB89PV140, add the current consumed by the EPROM which is connected to the top socket. * When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see section "s ELECTRICAL CHARACTERISTICS".) 4. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section "s MASK OPTIONS". Take particular care on the following point: * A pull-up resistor option is not provided for the MB89PV140. 5 MB89143A/144A s PIN ASSIGNMENT (MB89143A/4A only) (Top view) BZ P67 P66 P65 P64 P63 P62 P61 P60 N.C. P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P23 RST MODA X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC AVR AVSS P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P10 P11 P12 P13 P14 P15 P16 P17/ADST P30/INT0 P31/INT1 P32/SCK P33/SO P34/SI P35/EC P36 P37 P20 P21 P22 P70/X0A P71/X1A Note: When used as general-purpose ports, the P70/X0A and P71/X1A function as input-only ports. (DIP-64P-M01) 6 MB89143A/144A s PIN DESCRIPTION (MB89143A/4A only) Pin no. SDIP* 30 31 29 28 X0 X1 MODA RST B C Pin name Circuit type A Function Main clock oscillator pins Use a crystal oscillator. Operating mode selection pin Connect directly to VSS in normal operation. Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. "L" is output from this pin by an internal reset source. The internal circuit is initialized by the input of "L". This pin is with a noise canceller. General-purpose I/O ports These ports are a hysteresis input type. Also serve as an analog input. General-purpose I/O port This port is a hysteresis input type. Also serves as an A/D converter external activation. General-purpose I/O ports These ports are a hysteresis input type. Selectable either general-purpose input ports or the subclock oscillator pins by the mask option. These ports are a hysteresis input type when used as general-purpose input ports. General-purpose output ports General-purpose I/O ports These ports are a hysteresis input type. General-purpose I/O port This port is a hysteresis input type. Also serves as the external clock input for the 8/16-bit timer/counter. General-purpose I/O port This port is a hysteresis input type. Also serves as the serial data input for the 8-bit serial interface. General-purpose I/O port This port is a hysteresis input type. Also serves as the serial data output for the 8-bit serial interface. General-purpose I/O port This port is a hysteresis input type. Also serves as the serial transfer clock for the 8-bit serial interface. 54 to 61 P07/AN7 to P00/AN0 P17/ADST F 46 H 47 to 53 34, 33 P16 to P10 P70/X0A, P71/X1A H J 27, 35 to 37 38, 39 40 P23 to P20 P37, P36 P35/EC D H 41 P34/SI 42 P33/SO 43 P32/SCK * : DIP-64P-M01 (Continued) 7 MB89143A/144A (Continued) Pin no. SDIP* 44 Pin name P31/INT1 Circuit type E Function General-purpose I/O port This port is an N-ch open-drain output and hysteresis input type. Also serves as an external interrupt. The interrupt input is a hysteresis input type and with a built-in noise canceller. General-purpose I/O port This port is a hysteresis input type. Also serves as an external interrupt. The interrupt input is a hysteresis input type and with a built-in noise canceller. Buzzer output-only pin P-ch high-voltage open-drain output port P-ch high-voltage open-drain output port 45 P30/INT0 I 1 19 to 26, 11 to 18, 2 to 9 10 64 32 63 62 * : DIP-64P-M01 BZ P47 to P40, P57 to P50, P67 to P60 N.C. VCC VSS AVR AVSS G G -- -- -- -- -- Be sure to leave them open. Power supply pin Also serves as an A/D converter power supply. Power supply (GND) pin A/D converter reference voltage input pin A/D converter power supply pin Use this pin at the same voltage as VSS. 8 MB89143A/144A s I/O CIRCUIT TYPE Type Circuit X1 Remarks A * At an oscillation feedback resistor of approximately 1 M/5.0 V X0 Standby control signal B Hysteresis input * CMOS input C R P-ch * At an output pull-up resistor (P-ch) of approximately 50 k/5.0 V * CMOS hysteresis input N-ch Hysteresis input D P-ch * CMOS output N-ch E N-ch Port Hysteresis input Interrupt input With noise canceller * N-ch open-drain output * CMOS hysteresis input * The interrupt input is with a noise canceller. F P-ch * CMOS output * CMOS hysteresis input N-ch Port Hysteresis input Analog input (Continued) 9 MB89143A/144A (Continued) Type Circuit Remarks G P-ch * P-ch high-voltage open-drain output H P-ch P-ch * CMOS output * CMOS hysteresis input * Pull-up resistor optional (Only for P14 to P17 and P32 to P37) N-ch Port Hysteresis input I P-ch * CMOS output * CMOS hysteresis input * The interrupt input is with a noise canceller. N-ch Port Interrupt input Hysteresis input with noise canceller J X1A Port Hysteresis input * The oscillation feedback resistor is not provided. * CMOS hysteresis input when subclock is not used X0A Standby control signal Port Hysteresis input 10 MB89143A/144A s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s ELECTRICAL CHARACTERISTICS" is applied between VCC and VSS. (However, up to 7.0 V can be applied to P31/INT1 pin, regardless of VCC.) When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency(50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode. 11 MB89143A/144A s BLOCK DIAGRAM (MB89143A/4A only) Main clock oscillator (Max. 8 MHz) Clock controller High-voltage port 6 P70/X0A P71/X1A Subclock oscillator (32.768 kHz) High-voltage port 5 CMOS input port Internal bus 8 P40 to P47 8 P50 to P57 X0 X1 Buzzer output BZ 8 P60 to P67 Port 7 CMOS output port P20 to P23 Port 2 4 High-voltage port 4 Time-base timer CMOS I/O port CMOS I/O port 0 8-bit serial interface 8-bit A/D converter 8/16-bit timer/ counter Port 3 P07/AN7 to P00/AN0 AVR AVSS P17/ADST 8 P32/SCK P33/SO P34/SI 7 P10 to P16 CMOS I/O port 1 P35/EC RAM (256 x 8 bits) P30/INT0 External interrupt Port 3 P31/INT1 F2MC-8L CPU N-ch open-drain port Other pins V CC, V SS , M O D A , R S T ROM Note: The A/D converter is an 8-bit, 8-channel type. 12 MB89143A/144A s CPU CORE 1. Memory Space The microcontrollers of the MB89143A/144A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89143A/144A series is structured as illustrated below. MB89143A 0000 H I/O 0080 H RAM 256 0100 H Register 0180H 0180H 0100 H 0080 H 0000 H MB89144A I/O RAM 256 Register Not available Not available D000 H E000 H ROM 12 KB ROM 8 KB FFFF H FFFF H 13 MB89143A/144A 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code Initial value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 1, 1 Other bits are undefined. 16 bits PC A T IX EP SP PS The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 14 MB89143A/144A The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes b1 b0 "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set to 1 when an arithmetic operation results in 0. Cleared otherwise. Set to 1 if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 15 MB89143A/144A The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89143A/144A. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area 16 MB89143A/144A s I/O MAP Address 00H 01H 02H 03H 04H 05H, 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H to 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H to 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. 17 (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (W) T3CR T2CR T3DR T2DR SMR SDR ADC1 ADC2 ADDH ADDL PCR0 PCR1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R) SYCC STBC WDTE TBCR WPCR PDR3 DDR3 BUZR EIC PDR4 PDR5 PDR6 PDR7 Read/write (R/W) (W) (R/W) (W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register Vacancy System clock control register Standby control register Watchdog timer control register Time-base timer control register Watch prescaler control register Port 3 data register Port 3 data direction register Buzzer register External interrupt control register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Vacancy Timer 3 control register Timer 2 control register Timer 3 data register Timer 2 data register Serial mode register Serial data register A/D converter control register 1 A/D converter control register 2 A/D data register (H) A/D data register (L) Port input control register 0 Port input control register 1 Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy MB89143A/144A s ELECTRICAL CHARACTERISTICS (MB89143A/4A only) 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Power supply voltage Symbol VCC AVR VI1 Input voltage VI2 VI3 VO1 Output voltage VO2 "H" level total maximum output current "H" level total average output current "H" level maximum output current "H" level average output current "H" level maximum output current "H" level average output current "L" level total maximum output current "L" level total average output current "L" level maximum output current "L" level average output current Power consumption Operating temperature Storage temperature IOH IOHAV IOH IOHAV IOH IOHAV IOL IOLAV IOL IOLAV PD TA Tstg -- -- -- -- -- -- -- -- -- -- -- -- -40 -55 VCC + 0.3 -100 -75 -12 mA -6 -20 mA -10 50 30 12 mA 6 470 +85 +150 mW C C mA mA Average value (operating current x operation rate) P00 to P07, P10 to P17, P20 to P23, P30 to P37 SH-DIP64: DIP-64P-M01 V mA mA Average value (operating current x operation rate) P00 to P07, P30, P32 to P37, P10 to P17, P20 to P23 Average value (operating current x operation rate) P40 to P47, P50 to P57, P60 to P67, BZ Average value (operating current x operation rate) Rating Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VCC - 40 VSS - 0.3 Max. VSS + 7.0 VCC + 0.3 7 VCC + 0.3 VCC + 0.3 Unit V V V V V Remarks AVR VCC +0.3*1 P00 to P07, P10 to P17, P30, P32 to P37, P70, P71 P31 P40 to P47, P50 to P57, P60 to P67, BZ*2 P00 to P07, P10 to P17, P20 to P23, P30 to P37 P40 to P47, P50 to P57, P60 to P67, BZ*2 *1: Take care so that AVR does not exceed VCC + 0.3 V, and does not exceed VCC when power is turned on. *2: VI and VO must not exceed VCC + 0.3 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 18 MB89143A/144A 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Value Min. 4.0* 3.5* 2.5 1.5 Max. 6.0* 6.0* 6.0 6.0 VCC +85 Unit V V V V V C Remarks Normal operation assurance range* at highest gear speed Normal operation assurance range* at highest gear speed When in watch mode or subclock operation mode Retains the RAM state in stop mode Power supply voltage VCC A/D converter reference input voltage Operating temperature AVR TA 0.0 -40 * : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and "5. A/D Converter Electrical Characteristics." 6 5 Operation assurance range Operating voltage (V) 4 3 2 1 2 3 4 5 6 7 8 9 10 Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz) 2.0 1.3 1.0 0.8 0.66 0.57 0.5 0.44 0.4 Minimum execution time (instruction cycle) (s) Figure 1 Operating Voltage vs. Main Clock Operating Frequency Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 19 MB89143A/144A 3. DC Characteristics (AVR = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. Parameter Symbol Pin P00 to P07, P10 to P17, P30 to P37, P70, P71, X0, RST, X1, MODA P00 to P07, P10 to P17, P30 to P37, P70, P71, X0, RST, X1, MODA "H" level input VIHS voltage -- 0.8 VCC -- VCC + 0.3 V "L" level input voltage VILS -- VSS - 0.3 -- 0.2 VCC V Open-drain output pin application voltage VD1 P31 P00 to P07, P10 to P17, P20 to P23, P30 to P37 P40 to P47, P50 to P57, P60 to P67 P00 to P07, P10 to P17, P20 to P23, P30 to P37 -- VSS - 0.3 -- 7.0 V VOH1 "H" level output voltage VOH2 IOH = -2.0 mA 2.4 -- -- V Except P31 IOH = -10 mA 3.0 -- -- V VOL1 "L" level output voltage VOL2 ILI1 Input leakage current ILI2 Output leakage current IOL = 1.8 mA IOL = 4.0 mA 0 V < V1 < VCC -- -- -- -- -- -- 0.4 0.6 5 V V A Except pins with pull-up resistor Only for pins with pull-up resistor RST P00 to P07, P10 to P17, P30 to P37, P70, P71 P14 to P17, P32 to P37 P40 to P47, P50 to P57, P60 to P67 RST, P14 to P17, P32 to P37 VI = 0.0 V -200 -100 -50 A A k ILO1 VI = VCC - 35 V -- -- -10 Pull-up resistance RPULL VI = 0.0 V FCH = 8 MHz, VCC = 5.0 V, tinst = 0.5 s, when A/D conversion is stopped 25 50 100 Power supply current ICC1 VCC -- 9 15 mA Note: The power supply current is measured at the external clock. (Continued) 20 MB89143A/144A (Continued) (AVR = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. FCH = 8 MHz, VCC = 3.5 V, tinst = 8.0 s, when A/D conversion is stopped Sleep mode FCH = 8 MHz VCC = 5.0 V tinst = 0.5 s FCH = 8 MHz VCC = 3.5 V tinst = 8.0 s Parameter Symbol Pin ICC2 -- 1.5 2 mA ICCS1 -- 3 7 mA ICCS2 -- 1 1.5 mA A A ICCL FCL = 32.768 kHz VCC = 3.0 V Subclock mode FCL = 32.768 kHz VCC = 3.0 V Subclock mode FCL = 32.768 kHz VCC = 3.0 V * Watch mode * Main clock stop mode at dual-clock system FCL = 32.768 kHz TA = +25C * Subclock stop mode * Main clock stop mode at single-clock system FCH = 8 MHz, VCC = 5.0 V, TA = +25C, tinst = 0.5 s, when A/D conversion is activated FCH = 8 MHz, TA = +25C, when A/D conversion is activated FCH = 8 MHz, TA = +25C, when A/D conversion is stopped f = 1 MHz -- 50 150 ICCLS VCC ICCT -- 25 50 Power supply current -- 3 15 A ICCH -- -- 10 A ICCA -- 11.5 19.5 mA When the gear function is used, the power supply current varies with the measurement point. IR AVR IRH Other than AVSS, AVR, VCC, and VSS -- 200 -- A -- -- 10 A Input capacitance CIN -- 10 -- pF Note: The power supply current is measured at the external clock. 21 MB89143A/144A 4. AC Characteristics (1) Reset Timing (AVR = VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. -- -- 48 tXCYL 20 -- 40 -- 60 ns ns Parameter RST "L" pulse width RST noise limit width Symbol tZLZH tZLNC Note: tXCYL is the oscillation cycle (1/FCH) to input to the X0 pin. tZLZH tZLNC RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Power supply rising time Power supply cut-off time tR tOFF Symbol Condition -- -- Value Min. -- 1 Max. 50 -- Unit ms ms Remarks Power-on reset function only Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 2.0 V 0.2 V VCC tOFF 0.2 V 0.2 V 22 MB89143A/144A (3) Clock Timing (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Typ. Max. -- 32.768 -- 30.5 -- 15.2 -- 8 -- 500 -- -- -- 10 MHz kHz ns s ns External clock X0A X0, X0A -- -- -- -- ns ns External clock Parameter Clock frequency Clock cycle time Symbol FCH FCL tXCYL tLXCYL PWH PWL PWHL PWLL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 Condition Min. -- -- -- -- -- 2 -- 125 -- 30 Input clock pulse width Input clock rising/ falling time X0 and X1 Timings and Conditions tXCYL PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL Main Clock Conditions When a crystal or ceramic resonator is used When an external clock is used X0 X1 X0 X1 Open C0 C1 23 MB89143A/144A X0A and X1A Timings and Conditions tLXCYL PWHL tCR 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWLL Subclock Conditions When a crystal or ceramic resonator is used When an external clock is used X0A X1A X0A X1A Open RF RD C0 C1 Note: The subclock oscillator feedback resistor is connected externally in dual-clock products. (4) Instruction Cycle Parameter Symbol Value (typical) 4/FCH, 8/FCH, 16/FCH, 32/FCH Unit s s Remarks (4/FCH) tinst = 0.5 s when operating at FCH = 8 MHz tinst = 61.036 s when operating at FCL = 32.768 kHz Instruction cycle time tinst 2/FCL Note: When operating at 8 MHz, the cycle varies with the set execution time. 24 MB89143A/144A (5) Serial I/O timing (AVR = VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. 2 tinst* Internal shift clock mode -200 1/2 tinst* 1/2 tinst* 1 tinst* External shift clock mode 1 tinst* 0 1/2 tinst* 1/2 tinst* -- 200 -- -- -- -- 200 -- -- s ns s s s s ns s s Parameter Serial clock cycle time SCK SO time Valid SI SCK Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK Symbol tSCYC tSLOV tIVSH Pin SCK SCK, SO SI, SCK SCK, SI SCK SCK SCK, SO SI, SCK SCK, SI SCK valid SI hold time tSHIX tSHSL tSLSH tSLOV tIVSH SCK valid SI hold time tSHIX * : For information on tinst, see "(4) Instruction Cycle." Internal Shift Clock Mode tSCYC 2.4 V 0.8 V tSLOV 2.4 V 0.8 V tIVSH SI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.8 V SCK SO External Shift Clock Mode tSLSH 0.8 VCC 0.2 VCC 0.2 VCC tSLOV 2.4 V 0.8 V tIVSH SI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC tSHSL 0.8 VCC SCK SO 25 MB89143A/144A (6) Peripheral Input Timing (AVR = VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Peripheral input "H" pulse width 1 Peripheral input "L" pulse width 1 Symbol tILIH1 tIHIL1 Pin EC, ADST, INT0 to INT1 EC, ADST, INT0 to INT1 Condition -- -- Value Min. 2 tinst 2 tinst Max. -- -- Unit s s Remarks tIHIL1 INT0 to INT1, EC, ADST 0.2 VCC 0.8 VCC 0.2 VCC tILIH1 0.8 VCC (7) Peripheral Input Noise Limit Width (AVR = VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Peripheral input "H" level noise limit width 1 Peripheral input "L" level noise limit width 1 Symbol tIHNC1 tILNC1 Pin INT1, INT0 INT1, INT0 Value Min. 50 50 Typ. 100 100 Max. 250 250 Unit ns ns Remarks Note: The minimum values is always canceled, while values over the maximum value are not canceled. tILNC1 INT0, INT1 0.8 VCC 0.2 VCC 0.2 VCC tIHNC1 0.8 VCC 26 MB89143A/144A 5. A/D Converter Electrical Characteristics (VCC = 5.0 V10%, AVSS = VSS = 0.0 V, FCH = 8 MHz, TA = -40C to +85C) Value Condition Unit Remarks Pin Min. Typ. Max. -- -- -- -- AN0 to AN7 Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D conversion time Sense mode conversion time Analog port input current Analog input voltage Reference voltage Reference-voltage supply current Symbol -- -- -- -- VOT VFST -- -- -- IAIN -- -- IR -- -- -- -- -- -- -- -- -- -- -- -- -- AVSS - 1.5 LSB -- -- -- -- AVSS + 0.5 LSB 8 3.0 1.0 0.9 AVSS + 2.5 LSB bit LSB LSB LSB mV mV LSB s s A V V A AN0 to AN7 AVR - 3.5 LSB AVR - 1.5 LSB AVR + 0.5 LSB -- -- -- -- -- -- -- 0 4.5 -- -- 44 tinst 12 tinst -- -- -- 200 1.0 -- -- 10 AVR VCC -- AN0 to AN7 AVR==5.0 V VCC AN0 to AN7 -- -- AVR = 5.0 V AVR AVR Notes: * The smaller the | AVR - AVSS |, the greater the error would become relatively. * The output impedance of the external circuit for the analog input must satisfy the following conditions: Output impedance of the external circuit < Approx. 10 k If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 22 s at 8 MHz oscillation). Analog Input Equivalent Circuit Sample hold circuit . C =. 33 pF Analog input pin Comparator If the analog input impedance is 10 k or more, it is recommended to connect an external capacitor of approx. 0.1 F. . R =. 6 k Close for 8 instruction cycles after activating A/D conversion. Analog channel selector 27 MB89143A/144A 6. A/D Glossary * Resolution Analog changes that are identifiable with the A/D converter * Linearity error The deviation of the straight line connecting the zero transition point ("0000 0000" "0000 0001") with the full-scale transition point ("1111 1111" "1111 1110") from actual conversion characteristics * Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error The difference between actual and theoretical value This error is caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise. Theoretical I/O characteristics 1111 1111 1111 1110 Theoretical conversion value 1 LSB = Actual conversion value Digital output (1 LSB x N + VOT) AVR 256 VNT - (1 LSB x N + VOT) 1 LSB V(N+1)T - VNT 1 LSB Linearity error = Differential linearity error = -1 0000 0010 0000 0001 0000 0000 VOT Linearity error Total error = VNT - (1 LSB x N + 0.5 LSB) 1 LSB VNT V(N+1)T Analog input VFST 28 MB89143A/144A s MASK OPTIONS Part number Parameter Specification method 1 Clock mode selection Single-clock mode Dual-clock mode Pull-up resistors P14 to P17, P32 to P37 Power-on reset With Without Reset output With Without Pull-down resistors P40 to P47 P50 to P57 P60 to P67 MB89143A/144A Specify when ordering masking Can be set MB89PV140 101 102 MB89P147V1 Set in EPROM Can be set No. Single clock Dual clock 2 Specify by pin Without pull- Without pullCan be set per pin up resistor up resistor With power- With powerCan be set on reset on reset With reset output With reset output Can be set 3 With power-on rest 4 Can be set 5 Without pull-down resistor Without pull- Without pullWithout pull-down down down resistor resistor resistor s ORDERING INFORMATION Part number MB89143AP-SH MB89144AP-SH MB89P147V1P-SH Package 64-pin Plastic SH-DIP (DIP-64P-M01) Remarks 29 MB89143A/144A s PACKAGE DIMENSION 64-pin Plastic SH-DIP (DIP-64P-M01) 58.00 -0.55 2.283 -.022 +0.22 +.009 Note: Pins width and pins thickness include plating thickness. INDEX-1 17.000.25 (.669.010) INDEX-2 4.95 -0.20 .195 -.008 +0.70 +.028 0.70 -0.19 .028 -.007 +0.50 +.020 3.30 -0.30 .130 +0.20 +.008 -.012 +0.40 +.016 -.008 0.270.10 (.011.004) 1.378 -0.20 .0543 1.778(.0700) 0.470.10 (.019.004) 0.25(.010) M 19.05(.750) 0~15 1.00 -0 .039 +0.50 +.020 -.0 C 2001 FUJITSU LIMITED D64001S-c-4-5 Dimensions in mm (inches) 30 MB89143A/144A FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0107 (c) FUJITSU LIMITED Printed in Japan |
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